1. Field of the Invention
The present invention relates to a method of forming wiring. More particularly, the present invention relates to a method of forming wiring for electronic parts such as a semiconductor wafer, a wiring substrate and the like.
2. Description of the Related Art
There is provided a method of manufacturing a semiconductor device in which a rewiring pattern is formed on an electrode terminal formation face of a semiconductor wafer, an external connecting terminal is connected to the rewiring pattern and the semiconductor wafer is diced to individual pieces. FIG. 5 is a view showing a structure in which the face of the semiconductor wafer 10, on which the electrode terminal 12 is formed, is covered with the insulating layer 14, and the rewiring pattern 16, which is electrically connected to the electrode terminal 12, is formed on a surface of the insulating layer 14. Reference numeral 18 is a solder ball used as an external connecting terminal.
In the above method of manufacturing a semiconductor device, as it is necessary to form a fine rewiring pattern 16, a so-called “semi-additive” method by which a fine wiring can be formed is adopted so as to form the rewiring pattern 16.
FIGS. 6(a) to 6(e) are views showing a conventional method in which the rewiring pattern 16 is formed by the semi-additive method. Concerning the method of forming the rewiring pattern, refer to the U.S. Pat. No. 6,200,888 (corresponding to Japanese Unexamined Patent Publication No. 2001-28371), Japanese Unexamined Patent Publication No. 2001-127095 and Japanese Unexamined Patent Publication No. 2001-53075. FIG. 6(a) is a view showing a state in which an electrode formation face of the semiconductor wafer 10 is covered with the insulating layer 14 made of polyimide and the surface of the insulating layer 14 is coated with a seed layer 20 used for plating. The seed layer 20 can be formed by means of sputtering copper. In this connection, in order to improve the adhesion property of the wiring pattern to the insulating layer 14, chromium having an excellent adhesion property with respect to the insulating layer 14 is first sputtered and then copper is sputtered so as to form the seed layer 20.
FIG. 6(b) is a view showing a state of forming the resist pattern 22 on which the seed layer 20 is exposed. This seed layer 20 is formed, in a portion in which the wiring pattern is to be formed, by coating a surface of the seed layer 20 with photosensitive resist and exposing and developing it. Reference numeral 20a is an exposed portion of the seed layer 20.
FIG. 6(c) is a view showing a state in which electrolytic copper plating is performed when the seed layer 20 is used as an electricity feeding layer for plating, and the conductor 24 (copper plating), the width t of which is approximately 8μ, is formed by being heaped up in the exposed portion 20a. FIG. 6(d) is a view showing a state in which the resist pattern 22 is removed and the seed layer 20 coated with the resist pattern 22 is exposed. FIG. 6(e) is a view showing a state in which the seed layer 20, exposed onto the surface of the insulating layer 14, is etched so that the rewiring pattern 16 is formed.
FIGS. 7(a) to 7(c) are views showing a conventional example in which, after the conductor 24 has been heaped up in the exposed portion 20a on the seed layer 20, nickel plating is performed when the seed layer 20 is used as an electricity feeding layer so as to form a barrier layer 26. FIG. 7(a) is a view showing a state in which the barrier layer 26 is formed on a surface of the conductor 24. FIG. 7(b) is a view showing a state in which the resist pattern 22 is removed. FIG. 7(c) is a view showing a state in which the seed layer 20, formed on the surface of the insulating layer 14 and exposed to the outside, is removed and the rewiring pattern 16 is formed.
In the above case in which the rewiring pattern 16 is formed on the electrode terminal formation face of the semiconductor wafer, in the case where the wiring pattern is formed by the semi-additive method, the seed layer is provided and then the conductor, which becomes a wiring pattern, is formed and an unnecessary portion of the seed layer is removed by means of etching. In the above example, the seed layer 20 exposed onto the surface of the insulating layer 14 is removed by means of etching. The thickness of the seed layer 20 is approximately 1 μm or less, that is, the thickness of the seed layer 20 is very small. This means that the seed layer 20 can be easily removed by means of etching. Nevertheless, when the seed layer 20 is removed, the seed layer 20 is etched without coating the conductor 24 and the barrier layer 26 with resist or the like. The reason is that even when etching is conducted without protecting the conductor 24 by resist or the like, no problems are caused in the finished profile of the wiring pattern.
However, in the case where the pattern width and pattern interval of the rewiring pattern, which is to be formed on the electrode terminal formation face of the semiconductor wafer, and the pattern width and pattern interval of the wiring pattern, which is to be formed on the wiring substrate, become very small, such as not more than 20 μm, that is, in the case where the pattern width and pattern interval of the rewiring pattern and the wiring pattern are very fine, it becomes impossible to neglect that the conductor, which becomes a wiring pattern, is etched simultaneously when the seed layer is etched. Therefore, it becomes impossible to form a wiring pattern of predetermined finished accuracy.
FIGS. 8(a) and 8(b) are views showing a state in which the seed layer 20 and the conductor 24, which becomes a wiring pattern, are etched in the case of forming the wiring pattern by etching the seed layer 20. A broken line shows a position of the side of the conductor 24 before etching is conducted. FIG. 8(a) shows a case in which the seed layer 20 and the conductor 24 are provided, and FIG. 8(b) shows a case in which the seed layer 20, the conductor 24 and the barrier layer 26 are provided.
When the seed layer 20 is etched, an outer surface of the conductor 24 is exposed to an etchant and etched. In this case, there is a tendency for the lower layer side to be eroded as compared with the upper layer. Accordingly, as shown in the drawing, etching is performed in such a manner that the width of the seed layer 20 is reduced more than the width of the conductor layer 24. Therefore, even when the conductor 24 is etched to a predetermined width, the seed layer 20 is excessively etched. In the case shown in FIG. 8(b) in which the conductor 24 and the barrier layer 26 are made of different metals, the degree of erosion caused by etching on each layer is different. Therefore, a profile of the side of the wiring pattern cannot be formed uniformly.
As described above, the action of erosion caused by etching on the side of the conductor 24 in the case of etching the seed layer 20 cannot be neglected in the case of the wiring pattern, the pattern width of which is small, that is, the pattern width of which is not more than 20 μm. Accordingly, there is caused a problem that the wiring pattern is over-etched and the pattern width cannot be finished to a predetermined size. In the case where etching is controlled so that the wiring pattern cannot be over-etched, when intervals of the seed layer 20 between the wiring patterns are decreased, the seed layer between the wiring patterns cannot be completely etched and the wiring patterns are electrically short-circuited.
The above problems are caused when very fine wiring patterns are formed on the wiring substrate by the semi-additive method.